The present invention relates to a nonvolatile semiconductor memory device, especially a metal oxide nitride oxide semiconductor (MONOS) memory, and a fabrication method for such a memory device.
In recent years, with higher integration and lower cost of nonvolatile semiconductor memory devices, MONOS memory technology has been proposed in which a virtual ground array is adopted to allow local charge trapping.
MONOS memory cells have a 3-layer oxide nitride oxide (ONO) insulating film made of a bottom silicon oxide film, an intermediate silicon nitride film and a top silicon oxide film as a gate insulating film, and thus are different in structure from metal oxide semiconductor (MOS) transistors used for peripheral circuits, which have a silicon oxide film as a gate insulating film. For this reason, importance must be put in the technology on formation of the boundary between a memory cell area having the MONOS structure and a peripheral circuit area.
Hereinafter, an area where an ONO insulating film exists in formation of a gate electrode is defined as the memory cell area, while an area where the ONO insulating film has been removed in formation of a gate electrode is defined as the peripheral circuit area. In other words, the memory cell area and the peripheral circuit area are defined as distinguished from each other depending on whether or not an ONO insulating film exists. In some cases, therefore, gate electrodes formed continuously to constitute word lines for memory cells may extend from the memory cell area into the peripheral circuit area.
The ONO insulating film boundary does not necessarily agree with the boundary of wells.
A conventional nonvolatile semiconductor memory device and a fabrication method for the same will be described with reference to relevant drawings. See Japanese Laid-Open Patent Publication No. 2005-109297, for example.
FIG. 15 shows a plan configuration of a memory chip as a conventional nonvolatile semiconductor memory device. In FIG. 15, a gate insulating film is omitted for simplification.
As shown in FIG. 15, the memory chip includes a memory cell area 31 having a MONOS structure and a peripheral circuit area 32, and a memory cell boundary 33 defines the boundary between the memory cell area 31 and the peripheral circuit area 32. In the memory cell area 31, formed are MONOS memory cells each made of an active region 34 in a cell well and a gate electrode 35. In the peripheral circuit area 32, formed are MOS transistors each made of an active region 36 in a transistor well and a gate electrode 37. Although not shown in FIG. 15, an ONO insulating film is formed between the active region 34 and the gate electrodes 35 in the memory cell area 31, while a gate insulating film is formed between the active region 36 and the gate electrodes 37 in the peripheral circuit area 32. The gate electrodes 35 formed in the memory cell area 31 constitute word lines, which extend into the peripheral circuit area 32. Shallow trench isolation (STI) 38 surrounds the active region 34 in the cell well and the active regions 36 in the transistor well.
FIGS. 16A to 16C, 17A to 17C, 18A to 18C and 19A to 19C show cross-sectional configurations in the fabrication process steps for the memory chip as the conventional nonvolatile semiconductor device. Note that while the cross-sectional configurations of FIGS. 16A to 18C are common for both the section taken along line XVa-XVa and the section taken along line XVb-XVb in FIG. 15, FIG. 19A shows only the XVa-XVa section and FIGS. 19B and 19C show only the XVb-XVb section. Note also that the line XVb-XVb in FIG. 15 represents a section where no gate electrode 35 is formed.
First, as shown in FIG. 16A, a cell well 39 and a transistor well 40 are formed on a semiconductor substrate 30 in the memory cell area 31 and the peripheral circuit area 32, respectively. The STI 38 as an isolation film is then formed, and the active regions 34 and 36 are respectively formed in the cell well 39 and the transistor well 40. The transistor well 40 is actually composed of an n-type well, a p-type well, a deep n-type well and the like. The cell well 39 may be composed of a p-type well and, occasionally, a deep n-type well.
As shown in FIG. 16B, an ONO insulating film made of a bottom oxide film 41 having a thickness of about 5 nm, an intermediate nitride film 42 having a thickness of about 10 nm, and a top oxide film 43 having a thickness of about 15 nm is formed. The portion of the ONO insulating film formed in the memory cell area 31 constitutes a gate insulating film of MONOS memory cells.
As shown in FIG. 16C, using an ONO processing mask 44 formed above the cell well 39, the portion of the top oxide film 43 located above the transistor well 40 is removed by wet etching.
As shown in FIG. 17A, the ONO processing mask 44 is removed, and using the top oxide film 43 above the cell well 39 as a mask, the portion of the intermediate nitride film 42 located above the transistor well 40 is removed by wet etching.
The top oxide film 43 may be formed in a step of forming a gate oxide film of peripheral transistors, not forming in the step of forming the ONO insulating film shown in FIG. 16B. Otherwise, the top oxide film 43 may be formed in both the step of forming the ONO insulating film and the step of forming a gate oxide film of peripheral transistors. The portions of the top oxide film 43 and intermediate nitride film 42 formed above the transistor well 40 may be removed in succession by dry etching using the ONO processing mask 44 formed above the cell well 39.
As shown in FIG. 17B, the entire wafer is wet-etched with no mask used, to remove the portion of the bottom oxide film 41 formed above the transistor well 40. In this step, part or the entire of the top oxide film 43 above the cell well 39 is also removed simultaneously. The final top oxide film 43 will however be formed in the later step of forming a gate insulating film of peripheral transistors.
During the wet etching of the portion of the bottom oxide film 41 formed above the transistor well 40, the portion of the STI 38 at the boundary between the cell well 39 and the transistor well 40 is also partially removed, forming a step between the STI 38 and the transistor well 40. Moreover, if the wet etching is made using hydrofluoric acid and the like, the etching rate of the intermediate nitride film 42 is lower than that of the silicon oxide film constituting the bottom oxide film 41 and the top oxide film 43. Therefore, the top oxide film 43 overlying the intermediate nitride film 42 and the bottom oxide film 41 and the STI 38 underlying the intermediate nitride film 42 may be etched away at their end portions, leaving the intermediate nitride film 42 overhanging. FIG. 17C shows a cross-sectional configuration illustrating the thus-etched boundary between the cell well 39 and the transistor well 40.
As shown in FIG. 18A, a gate oxide film 45, which is to be a gate insulating film of MOS transistors used in peripheral circuits is formed on the transistor well 40 by thermal oxidation. Although the gate oxide film is actually made of a plurality of layers in many cases, it is simply shown as a single-layer film in FIG. 18A. During the formation of the gate oxide film 45, the thickness of the top oxide film 43 above the cell well 39 increases a little although illustration on this increase is omitted.
In the step of forming the gate oxide film 45, the gate oxide film 45 is formed while the intermediate nitride film 42 is kept overhanging. Although the thicknesses of the top oxide film 43, the bottom oxide film 41, the intermediate nitride film 42 and the STI 38 respectively increase a little during the formation of the gate oxide film 45 by thermal oxidation, the rate of oxidation of these films is significantly low compared with that of the active region 36 in the transistor well 40 made of silicon, and thus the intermediate nitride film 42 is kept overhanging. Note that illustration is omitted on the increase in the thicknesses of the top oxide film 43, the bottom oxide film 41, the intermediate nitride film 42 and the STI 38.
As shown in FIG. 18B, polysilicon 46, which is to be gate electrodes of MONOS memory cells and MOS transistors, is deposited on the top surface of the resultant semiconductor substrate 30.
In the step of forming the polysilicon 46, as shown in FIG. 18C, which shows the case of FIG. 17C where the intermediate nitride film 42 overhangs, the polysilicon 46 is formed even under the overhang to bury the boundary between the ONO insulating film and the gate oxide film 45.
As shown in FIG. 19A, the polysilicon 46 is etched to form the gate electrode 35 of MONOS memory cells and the gate electrode 37 of MOS transistors.
According to the conventional technique, however, the portion of the STI 38 removed during the removal of the portion of the bottom oxide film 41 above the transistor well 40 forms a depression at the boundary between the ONO insulating film and the gate oxide film 45. Having such a depression, a post-etch residue may be produced in the depression at the etching of the polysilicon 46.
Since polysilicon is good in deposition in a depression, it can be efficiently formed in the depression existing at the boundary between the ONO insulating film and the gate oxide film 45, as shown in FIGS. 18B and 18C. In particular, as shown in FIG. 18C, which shows the case that the intermediate nitride film 42 overhangs, polysilicon is deposited even under the overhang of the intermediate nitride film 42. The thus-formed polysilicon 46 is likely to produce a post-etch residue at the etching. Because the overhang serves as a mask, the underlying portion is inevitably left unetched. Production of such a post-etch residue depends on the etching conditions of the polysilicon 46 and the shape and length of the overhang of the intermediate nitride film 42.
FIG. 19B shows a cross-sectional configuration of a region in which the memory cell area 31 has no gate electrode 35.
As shown in FIG. 19B, a depression is generally formed at the boundary between the ONO insulating film and the gate oxide film 45 and a post-etch residue of the polysilicon 46 is left behind like a sidewall on the bottom of the depression even when the intermediate nitride film 42 does not overhang, forming a polysilicon residue 101.
The polysilicon residue 101 shown in FIG. 19B may be in contact with an extension of the gate electrode 35, which constitutes a word line in the memory cell area 31, into the peripheral circuit area 32, and this may possibly cause a short between gate electrodes in the memory cell area 31. Also, such a residue may come off and becomes particles.
FIG. 19C shows a cross-sectional configuration of a region in which the memory cell area 31 has no gate electrode 35 and the intermediate nitride film 42 overhangs.
As shown in FIG. 19C, the portion of the polysilicon 46 formed under the overhang of the intermediate nitride film 42 is left unetched at the etching of the polysilicon 46, forming a polysilicon residue 101 as a post-etch residue.
The polysilicon residue 101 shown in FIG. 19C may be in contact with an extension of the gate electrode 35, which constitutes a word line in the memory cell area 31, into the peripheral circuit area 32, and this may possibly cause a short between gate electrodes in the memory cell area 31. Also, such a residue may come off and becomes particles.
As described above, the polysilicon residue 101 as a post-etch residue of the polysilicon 46 may be formed, and this may cause a short between gate electrodes or be lifted off to become a source of particles. In either case, the yield will be degraded.